6.串口发送模块的使用2

uart_tx_data

//使用串口发送5个字节(40位)的数据到电脑
module uart_tx_data(
    Clk,
    Reset_n,
    Data40,
    Trans_Go,
    uart_tx,
    Trans_Done
);
    input Clk;
    input Reset_n;
    input [39:0]Data40;
    input Trans_Go;
    output uart_tx;
    output reg Trans_Done;
    
    reg [7:0] Data;
    reg Send_Go;
    wire Tx_done;
    
    uart_byte_tx DUT(
        .Clk(Clk),
        .Reset_n(Reset_n),
        .Data(Data),
        .Send_Go(Send_Go),
        .Baud_set(4),
        .uart_tx(uart_tx),
        .Tx_done(Tx_done)
     );
     
     reg [2:0]state;
     always@(posedge Clk or negedge Reset_n)
     if(!Reset_n)begin
        state <= 0;
        Data <= Data40[7:0];
        Send_Go <= 0;
        Trans_Done <= 0;
     end
     else if(state == 0)begin
        Trans_Done <= 0;
        if(Trans_Go)begin
            Data <= Data40[7:0];
            Send_Go <= 1;
            state <= 1;
        end
        else begin
            Data <= Data;
            Send_Go <= 0;
            state <= 0;
        end
     end
     else if(state == 1)begin
        if(Tx_done)begin
            Data <= Data40[15:8];
            Send_Go <= 1;
            state <= 2;
        end
        else begin
            Data <= Data;
            Send_Go <= 0;
            state <= 1;
        end
     end
     else if(state == 2)begin
        if(Tx_done)begin
            Data <= Data40[23:16];
            Send_Go <= 1;
            state <= 3;
        end
        else begin
            Data <= Data;
            Send_Go <= 0;
            state <= 2;
        end
     end
      else if(state == 3)begin
        if(Tx_done)begin
            Data <= Data40[31:24];
            Send_Go <= 1;
            state <= 4;
        end
        else begin
            Data <= Data;
            Send_Go <= 0;
            state <= 3;
        end
     end
     else if(state == 4)begin
        if(Tx_done)begin
            Data <= Data40[39:32];
            Send_Go <= 1;
            state <= 5;
        end
        else begin
            Data <= Data;
            Send_Go <= 0;
            state <= 4;
        end
     end
     else if(state == 5)begin
        if(Tx_done)begin
            Send_Go <= 0;
            Trans_Done <= 1;
            state <= 0;
        end
        else begin
            Data <= Data;
            Send_Go <= 0;
            state <= 5;
        end
     end
            
     
endmodule

uart_tx_data_tb

`timescale 1ns / 1ps

module uart_tx_data_tb();
    reg Clk;
    reg Reset_n;
    reg[39:0]Data40;
    reg Trans_Go;
    wire uart_tx;
    wire Trans_Done;
    uart_tx_data uart_tx_data(
        .Clk(Clk),
        .Reset_n(Reset_n),
        .Data40(Data40),
        .Trans_Go(Trans_Go),
        .uart_tx(uart_tx),
        .Trans_Done(Trans_Done)
    );
    
    initial Clk = 1;
    always#10 Clk = ~Clk;
    
    initial begin
        Reset_n = 0;
        Data40 = 0;
        Trans_Go = 0;
        #201;
        Reset_n = 1;
        #200;
        Data40 = 40'h123456789a;
        Trans_Go = 1;
        #20;
        Trans_Go = 0;
        @(posedge Trans_Done);
        #200000;
    
        Data40 = 40'ha987654321;
        Trans_Go = 1;
        #20;
        Trans_Go = 0;
        @(posedge Trans_Done);
        #200000;
        $stop;
    end
endmodule

仿真波形

uart_tx_data_test

//使用串口每隔10ms发送5个字节(40位)的数据到电脑，数的大小是每次加1
module uart_tx_data_test(
    Clk,
    Reset_n,
    uart_tx
    );
    input Clk;
    input Reset_n;
    output uart_tx;
    
    reg Trans_Go;
    reg[39:0] Data40;
    
    uart_tx_data uart_tx_data(
        .Clk(Clk),
        .Reset_n(Reset_n),
        .Data40(Data40),
        .Trans_Go(Trans_Go),
        .uart_tx(uart_tx),
        .Trans_Done(Trans_Done)
    );
     // 100ms 的计数器
    reg[24:0] counter;
    //reg [18:0] counter;  //仿真用10ms  
    always@(posedge Clk or negedge Reset_n)
    if(!Reset_n)
        counter <= 0;
    else if(counter == 4999999)
    //(counter == 499999)//仿真用10ms
        counter <= 0;
    else
        counter <= counter + 1;
    
     always@(posedge Clk or negedge Reset_n)
    if(!Reset_n)
        Trans_Go <= 0;
    else if(counter == 1)
        Trans_Go <= 1;
    else
        Trans_Go <= 0;
        
    always@(posedge Clk or negedge Reset_n)
    if(!Reset_n)
        Data40 <= 1;
    else if(Trans_Done)
        Data40 <= Data40 + 1'b1; 
endmodule

uart_tx_data_test_tb

`timescale 1ns / 1ps

module uart_tx_data_test_tb();
    reg Clk;
    reg Reset_n;
    wire uart_tx;
    uart_tx_data_test uart_tx_data_test(
        .Clk(Clk),
        .Reset_n(Reset_n),
        .uart_tx(uart_tx)
    );
    
    initial Clk = 1;
    always#10 Clk = ~Clk;
    
    initial begin 
       Reset_n = 0;
       #201; 
       Reset_n =  1;
       #50000000;
    end
endmodule

仿真波形

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